1. Field of the Invention
The present invention relates to a reprogrammable nonvolatile semiconductor device which has a gate electrode structure comprised of at least two layers and a method of manufacturing the same, and more particularly to a nonvolatile memory such as an EPROM and a method of manufacturing the same.
2. Description of the Related Art
FIG. 1 is a view showing the planar pattern of a conventional ultraviolet erasure type EPROM which has e.g. a double-layered gate electrode structure, FIG. 2 is a sectional view taken along line II--II in FIG. 1, and FIG. 3 is a circuit diagram corresponding to the EPROM shown in FIGS. 1 and 2. Referring to FIGS. 1 and 2, reference numeral 1 denotes a memory cell, 2 an element isolation region, 3 a floating gate electrode, 4 a control gate electrode serving as a word line, 5 a contact hole, 6 a bit line formed of aluminum, 10 a p-type substrate, 11 an n.sup.+ -type source, 12 an n.sup.+ -type drain, and 13 an insulating BPSG layer. The floating gate electrode 3 and the control gate electrode 4 jointly constitute a double-layered gate electrode structure. The n.sup.+ -type source 11 and the n.sup.+ -type drain 12 are a common source and a drain, respectively, which are used in common to adjacent memory cells. The common source 11 is a diffusion layer which is formed in a surface region of the p.sup.+ -type substrate 10 in parallel to the control gate electrode 4. The contact hole 5 is used in common to the adjacent memory cells. To write information in the memory cell, a high voltage is applied to the control gate electrode 4 and the drain 12. To be more specific, channel electrons are generated by the application of the high voltage, and electrons are injected into the floating gate electrode 3. As a result, the threshold voltage of the cell transistor is raised, thus allowing the information to be written in the memory cell.
In the memory mentioned above, the contact hole 5 and the element isolation region 2 have to be spaced apart from each other by a certain distance (an allowance for misalignment) which is required in the masking step of the manufacture. Likewise, the contact hole 5 and the floating gate electrode 3 have to be spaced apart from each other by a certain distance. Due to the necessity of providing such allowances, the contact hole 5 cannot be enoughly scaled or reduced proportionally. Thus, each memory cell is prevented from being miniaturized or having a large capacity. In addition, one half of a common source diffusion layer has to be assigned to each memory cell.
FIG. 4 is a sectional view showing the structure of a conventional contactless EPROM, and FIG. 5 is a circuit diagram of the contactless EPROM. Referring to FIGS. 4 and 5, reference numeral 21 denotes a p-type substrate, 22 a bit line formed by an n.sup.+ -type embedded diffusion layer (i.e., a source/drain diffusion layer), 23 a field insulation film (i.e., an element-isolation oxide film), 24 a gate insulation film, 25 an insulation film between a floating gate and a control gate, 26 a floating gate, 27 a control gate serving as a word line, and 28 a memory cell. In order to provide a large capacity for this contactless EPROM, the source/drain diffusion layer 22 is buried under the field insulation film 23 located between the adjacent memory cells which use the control gate 27 in common. No contact hole is provided for the buried diffusion layer 22. Due to this cell structure, the EPROM does not have to have a contact hole or a common source diffusion layer, such as that shown in FIG. 3, so that the EPROM can be miniaturized and have a large capacity. The cell size of the contactless EPROM shown in FIG. 4 is not more than 70% of the cell size of the conventional EPROM. However, this contactless EPROM has to be provided with a selection circuit (not shown) by which the buried diffusion layer 22 is selectively used as either a source or a drain in accordance with the operating condition of each memory cell. Thus, the contactless EPROM is disadvantageous, in that the peripheral circuit portions (i.e., the circuit portions other than each memory cell) are inevitably complicated. In addition, the more the EPROM is miniaturized, the worse the selection characteristic of the selection circuit becomes.